JEE Main · 2025 · 07 Apr 2025 · Shift 2 · Semiconductors

The upper AND gate produces $Y_1=A\cdot B$, while the OR gate receives $\overline{A}$ (through the inverter) and $B$, giving $Y_2=\overline{A}+B$. The final NAND gate gives $Y=\overline{Y_1\cdot Y_2}$, so the output is low only when both $Y_1$ and $Y_2$ are high. Here $Y_2=\overline{A}+B$ equals $1$ except when $A=1,B=0$, while $Y_1=A\cdot B$ equals $1$ only when $A=1,B=1$. The two are simultaneously high only for $A=1$ and $B=1$, and there the NAND output falls to zero. Thus the output is zero when $A=1$ and $B=1$.