JEE Main · 2012 · 29 Apr 2012 · Offline · Semiconductors

The four NAND gates are wired so that the output reproduces the exclusive-OR of the two inputs. Tracing the logic, the first gate gives $\overline{A\cdot B}$, the two middle gates combine this with $A$ and with $B$ respectively, and the final gate recombines their outputs; working the levels through for each input pair gives output $0$ for inputs $0,0$, output $1$ for $0,1$, output $1$ for $1,0$ and output $0$ for $1,1$. That is the exclusive-OR truth table, in which the output is high only when the two inputs differ.