JEE Main · 2023 · 29 Jan 2023 · Shift 2 · Semiconductors

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For the given logic gates combination, the correct truth table will be
  1. (A)A=0, B=0, X=1; A=0, B=1, X=0; A=1, B=0, X=0; A=1, B=1, X=0
  2. (B)A=0, B=0, X=0; A=0, B=1, X=1; A=1, B=0, X=1; A=1, B=1, X=0✓ Correct
  3. (C)A=0, B=0, X=1; A=0, B=1, X=0; A=1, B=0, X=1; A=1, B=1, X=0
  4. (D)A=0, B=0, X=0; A=0, B=1, X=1; A=1, B=0, X=1; A=1, B=1, X=1

Answer: (B)

Solution

Tracing the network, the top AND gate receives from the inverter together with , giving , while the bottom AND gate receives together with from the second inverter, giving . The OR gate then forms , which is the exclusive-OR of the inputs. The output is when the inputs are equal and when they differ, so for the input pairs .

JEE Main · 2023 · 29 Jan 2023 · Shift 2 · Single correct option

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